Before a chip is cut or packaged, it needs to undergo electrical testing on the entire wafer. This step is commonly referred to as CP (Chip Probing), also commonly known as Wafer Sort or Wafer Test. What parameters are tested in CP testing? ”The focus of different chips is completely different, what are the specific differences?
1. For memory chips such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and Flash (Flash Memory), CP testing will focus on read and write functionality, address decoding, storage unit defects, hold time, erase/write capability, interference failure, and redundancy repair. Common algorithms include March Test, Read Disturb, Program Disturb, Erase Disturb, etc. Many memories also perform repairs during the CP phase, replacing bad rows and columns with redundant ones.
2. Analog and mixed signal chips focus on ADC (Analog to Digital Converter), DAC (Digital to Analog Converter), operational amplifier, power management chip, etc. CP will pay attention to Offset Error, Gain Error, INL (Integral Non Linear), DNL (Differential Non Linear), SNR (Signal to Noise Ratio), SINAD (Signal to Noise and Distance Ratio), ENOB (Effective Number of Bits), PSRR (Power Supply Rejection Ratio), etc., power suppression ratio, etc.
3. For RF (Radio Frequency) chips, the focus of testing will shift to frequency domain performance, such as S-parameters (Scattering Parameters), Gain (Gain), Noise Figure (Noise Figure), Output Power (Output Power), P1dB (1 dB Compression Point), IP3 (Third Order Intercept Point), ACPR (Adjacent Channel Power Ratio), EVM (Error Vector Magnitude), etc. RF CP testing is typically sensitive to probes, calibration, shielding, fixtures, and testing time.
4. For power devices such as MOSFET, IGBT (Insulated Gate Bipolar Transistor), SiC (Silicon Carbide), and GaN (Gallium Nitride), CP will focus on voltage resistance, on resistance, leakage, threshold, capacitance, and gate charge. Common projects include BVDSS (Drain Source Breakdown Voltage), IDSS (Drain Source Leakage Current), IGSS (Gate Source Leakage Current), VGS (th) (Gate Threshold Voltage), RDS (on) (Drain Source On Resistance), Qg (Gate Charge), etc.
The CP testing checklist is determined by the product type, process platform, yield risk, testing cost, customer requirements, and reliability level. The truly mature mass production testing is to find the optimal solution between sufficient quality assurance and acceptable testing costs. Whether a chip can be packaged, what level it can be sold at, and whether it can enter the automotive, communication, industrial, or consumer electronics markets are often written into the wafer diagram at the moment of CP testing.

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